Quick answer

Half adder: two bits in, sum and carry out. Full adder: adds carry-in. Chained full adders form multi-bit ripple-carry adders.

Rules

  • Half adder: no carry_in (column 0 or isolated demo)
  • Full adder: A, B, carry_in → sum, carry_out
  • Ripple chain: carry_out[i] → carry_in[i+1]

Introduction

Learn the math on the Binary Addition Calculator first; circuits mirror that logic with wires instead of pencil marks.

This article assumes you can add binary by hand. If not, pause here and practice manual carries before reading schematics.

See binary addition formulas for XOR and majority expressions that match gate-level sum and carry outputs.

For carry chains on paper, review binary addition with carry so propagation in hardware feels familiar.

Half and full adders

Half adder: inputs A and B; outputs sum (A XOR B) and carry (A AND B). Used where no carry_in exists, such as the least significant bit in some designs.

Full adder: three inputs (A, B, carry_in) and two outputs (sum, carry_out). Implements the general column formula with carry propagation.

Truth tables for full adders line up with the 0+0+1 and 1+1+1 cases you practice in homework.

Arithmetic circuits in processors repeat these cells across bit widths (8, 16, 32, 64) with timing and overflow detection added around the core.

Digital systems courses breadboard small adders before moving to FPGAs; the numeric results should still match manual addition.

Ripple-carry adder and beyond

  • Connect full adders in series: carry_out → carry_in
  • Sum outputs form the result bus bit by bit
  • Overflow detection watches carry_out beyond MSB or sign rules in signed designs

Ripple-carry is simple to teach but slower for wide operands. Carry-lookahead and other schemes trade gates for speed; introductory classes still start with ripple.

Boolean algebra describes the AND/OR/XOR networks inside each full adder cell. The algebra is the same information as the formula page, rearranged.

Compare simulator waveforms to calculator output for the same operand pair to confirm your schematic matches software expectations.

Step-by-step guide

  1. Draw one full adder block. Label A, B, carry_in, sum, carry_out. Relate each line to a column on paper.
  2. Chain N full adders. Match bit order: rightmost cell is LSB. Wire carries leftward.
  3. Simulate 4-bit addition in software. Use lab tools or the home calculator to set expected numeric output before hardware debug.
  4. Trace a ripple example bit by bit. Follow 0111 + 0001 through each cell’s sum and carry pins.
  5. Discuss delay and overflow in lab reports. Connect final carry-out to course definitions of overflow or extension bits.

Lab and study tips

Simulate 1011 + 1101 in software, note sum 11000, then compare to breadboard LEDs or FPGA outputs bit by bit.

When a waveform disagrees, re-run manual addition and decimal verification before rewiring; many lab bugs are operand wiring order, not gate failure.

Document how each full adder column maps to your handwritten carry marks for grading clarity.